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AD9524SLASHPCBZ中文資料
AD9524SLASHPCBZ數(shù)據(jù)手冊規(guī)格書PDF詳情
GENERAL DESCRIPTION
The AD9524 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. The AD9524 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise require ments necessary for acceptable data converter SNR performance.
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±150 ps
6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
6 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ? period of VCO output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: ?160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I2C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with external VCXO
Phase detector rate of 300 kHz to 75 MHz
Redundant reference inputs
Auto and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF synthesizers
PLL2
Phase detector rate of up to 250 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
AD |
16+ |
LFCSP48 |
10000 |
進口原裝現(xiàn)貨/價格優(yōu)勢! |
|||
AD |
17+ |
LFCSP48 |
6200 |
100%原裝正品現(xiàn)貨 |
|||
AD |
25+23+ |
LFCSP48 |
43171 |
絕對原裝正品現(xiàn)貨,全新深圳原裝進口現(xiàn)貨 |
|||
AD |
24+ |
QFN |
80000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
|||
ADI(亞德諾)/LINEAR |
2447 |
LFCSP-48 |
315000 |
260個/托盤一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長 |
|||
ADI/亞德諾 |
QFN |
6698 |
|||||
ADI |
20+ |
QFN-48 |
932 |
就找我吧!--邀您體驗愉快問購元件! |
|||
ADI(亞德諾)/LINEAR |
2021+ |
LFCSP-48 |
499 |
||||
ADI(亞德諾) |
23+ |
NA |
20094 |
正納10年以上分銷經(jīng)驗原裝進口正品做服務做口碑有支持 |
|||
ADI/亞德諾 |
23+ |
LFCSP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
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Analog Devices 亞德諾半導體技術有限公司
(Analog Devices,簡稱ADI)成立于1965年,總部位于美國馬薩諸塞州諾丁漢,是全球領先的高性能模擬、混合信號和數(shù)字信號處理集成電路(IC)設計與制造公司。ADI致力于為各種應用提供創(chuàng)新的解決方案,涵蓋通信、工業(yè)、汽車、醫(yī)療、消費電子和數(shù)據(jù)中心等多個領域。 公司以其強大的研發(fā)實力和專業(yè)技術著稱,擁有廣泛的產(chǎn)品組合,包括放大器、轉(zhuǎn)換器、傳感器和處理器等,能夠滿足客戶在信號處理和控制方面的需求。ADI的產(chǎn)品被廣泛應用于數(shù)據(jù)測量、無線通信、音頻處理、視頻監(jiān)控以及自動化和控制系統(tǒng)等領域。 模擬器件公司始終致力于推動技術創(chuàng)新,憑借強大的科技實力,為客戶提供高效、可靠的解決方案,幫助他們提高