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FUNCTIONAL OVERVIEW

SUPERNET 3 is a 208-pin CMOS integration of FDDI MAC, PHY, Address Filter, and clock generation and recovery functions. It is the third generation FDDI offering from AMD which integrates the SUPERNET 2 family of chips into a single-chip solution. Refer to the SUPERNET 2 data book (PID 15502C) for basic feature descriptions.

DISTINCTIVE CHARACTERISTICS

■ Compliant with the ANSI X3T9.5/ISO 9314 specification

— 100 Mbps data rate

— Timed token-passing protocol

— Ring topology

■ Complete memory management

— Supports 256K bytes of local frame buffer memory

— Supports buffer memory bandwidths of 200 Mbps and 400 Mbps

— Tag-Mode: minimum latency/highest performance buffer memory management, ideal for adapter card designs

■ ANSI-compliant TP-PMD Stream Cipher Scrambling/Descrambling

■ Full duplex operation: 200 Mbps continuous data rate

■ Supports both fiber optic and copper twistedpair media

■ Diagnostic features

— Built in Self Test (BIST) in Address Filter, Physical Layer Controller with Scrambler

■ Hardware Physical Connection Management support

■ Low power consumption—reduction of more than 25 from SUPERNET 2 solution