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General Description

The A65H73361 and A65H83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4Mb SRAMS built using high performance CMOS process.

Features

■ Fast access times: 2.5/3.0/3.5ns

■ 128k x 36 or 256k x 18 organizations

■ CMOS technology

■ Register to register synchronous operation with self-timed late write

■ Single +3.3V ±5 power supply

■ Individual byte write and global write

■ HSTL input & output levels

■ Boundary scan(JTAG) IEEE 1149.1 compatible

■ Asynchronous output enable

■ Sleep mode (ZZ)

■ Programmable impedance output drivers

■ JEDEC Standard pinout and boundary scan order

■ 7 x 17 bump plastic ball grid array (PBGA) package