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Description

The Atmel ? | SMART ARM926EJ-S?-based SAM9G46 embedded microprocessor unit (eMPU) features the frequently requested combination of user interface functionality and high data rate connectivity, including LCD controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400 MHz and multiple 100+ Mbps data rate peripherals, the SAM9G46 provides adequate performance and bandwidth to the network or local storage media.

Features

? 400 MHz ARM926EJ-S ARM? Thumb? Processor

? 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU

? Memories

? 4-port, 4-bank DDR2/LPDDR Controller

? External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash?,

SLC NAND Flash with ECC

? 64 Kbytes internal SRAM, single-cycle access at system speed or processor speed through TCM interface

? 64 Kbytes internal ROM, embedding bootstrap routine

? Peripherals

? LCD Controller (LCDC) supporting STN and TFT displays up to 1280*860

? ITU-R BT. 601/656 Image Sensor Interface (ISI)

? Dual High Speed USB Host and a High Speed USB Device with On-Chip Transceivers

? 10/100 Mbps Ethernet MAC Controller (EMAC)

? Two High Speed Memory Card Hosts (SDIO, SDCard, e.MMC and CE ATA)

? AC’97 Controller (AC97C)

? Two Master/Slave Serial Peripheral Interfaces (SPI)

? 2 Three-channel 16-bit Timer/Counters (TC)

? Two Synchronous Serial Controllers (I2S mode)

? Four-channel 16-bit PWM Controller

? 2 Two-wire Interfaces (TWI)

? Four USARTs with ISO7816, IrDA, Manchester and SPI modes; one Debug Unit (DBGU)

? 8-channel 10-bit ADC with 4-wire Touchscreen support

? Write Protected Registers

? Cryptography

? True Random Number Generator (TRNG)

? AES256-, 192-, 128-bit Key Algorithm

? TDES Compliant with FIPS PUB 46-3 Specifications

? SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2

? System

? 133 MHz twelve 32-bit layer AHB Bus Matrix

? 39 DMA Channels

? Boot from NAND Flash, SDCard, DataFlash or serial DataFlash

? Reset Controller (RSTC) with on-chip Power-on Reset

? Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators

? Internal Low-power 32 kHz RC Oscillator

? One PLL for the system and one 480 MHz PLL optimized for USB High Speed

? Two Programmable External Clock Signals

? Advanced Interrupt Controller (AIC)

? Periodic Interval Timer (PIT), Watchdog Timer (WDT), Real-time Timer (RTT) and Real-time Clock (RTC)

? I/O

? Five 32-bit Parallel Input/Output Controllers

? 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input

? Package

? 324-ball TFBGA - 15 x 15 x 1.2 mm, 0.8 mm pitch