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Features

■ Powerline communication solution

? Integrated powerline modem PHY

? Frequency shift keying modulation

? Configurable baud rates up to 2400 bps

? Powerline optimized network protocol

? Integrates data link, transport, and network layers

? Supports bidirectional half duplex communication

? 8-bit CRC error detection to minimize data loss

? I2C enabled powerline application layer

? Supports I2C frequencies of 50, 100, and 400 kHz

? Reference designs for 110 V/240 V AC and 12 V/24 V AC/DC Powerlines

? Reference designs comply with CENELEC EN 50065-1:2001 and FCC Part 15

■ Powerful Harvard-architecture Processor

? M8C processor speeds to 24 MHz

? Two 8x8 multiply, 32-bit accumulate

■ Programmable system resources (PSoC? Blocks)

? 12 Rail-to-Rail Analog PSoC Blocks provide:

? Up to 14-bit ADCs

? Up to 9-bit DACs

? Programmable gain amplifiers

? Programmable filters and comparators

? 16 Digital PSoC Blocks provide:

? 8 to 32-bit Timers, Counters, and PWMs

? CRC and PRS Modules

? Up to four full duplex UARTs

? Multiple SPI? masters or slaves

? Connectable to all GPIO Pins

? Complex peripherals by combining blocks

■ Flexible on-chip memory

? 32 KB flash program storage 50,000 erase or write cycles

? 2 KB SRAM data storage

? EEPROM emulation in flash

■ Programmable pin configurations

? 25 mA sink, 10 mA source on all GPIOs

? Pull-up, Pull-down, high Z, strong, or open drain drive Modes on all GPIO

? Up to 12 analog inputs on all GPIOs

? Configurable interrupt on all GPIOs

■ Additional system resources

? I2C slave, master, and multi-master to 400 kHz

? Watchdog and sleep timers

? User-configurable low-voltage detection

? Integrated supervisory circuit

? On-chip precision voltage reference

■ Complete development tools

? Free development software (PSoC Designer?)

? Full-featured in-circuit emulator (ICE) and programmer

? Full-speed emulation

? Complex breakpoint structure

? 128 KB trace memory

? Complex events

? C Compilers, assembler, and linker