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FEATURES

■ Access Times of 35ns (SRAM) and 70ns (FLASH)

■ JEDEC Standard, Hermetic Ceramic Package, 32 pin DIP (Package 300)

■ 256Kx8 SRAM

■ 256Kx8 5V FLASH

■ Memory Map

Flash Memory: 0H-3FFFFH

SRAM: 40000H-7FFFFH

■ Low Power CMOS

■ Commercial, Industrial and Military Temperature Ranges

■ TTL Compatible Inputs and Outputs

■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

FLASH MEMORY FEATURES

■ 10,000 Erase/Program Cycles

■ Sector Architecture

? 8 equal size sectors of 16KBytes each

? Any combination of sectors can be concurrently erased. Also supports full chip erase

■ Data Retention, 10 Years at 125°C

■ 5 Volt Programming; 5V ± 10 Supply

■ Embedded Erase and Program Algorithms

■ Hardware and Software Write Protection

■ Page Program Operation and Internal Program Control Time