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56F802 General Description

? Up to 30 MIPS operation at 60MHz core frequency

? Up to 40 MIPS operation at 80MHz core frequency

? DSP and MCU functionality in a unified, C-efficient architecture

? MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes

? Hardware DO and REP loops

? 6-channel PWM Module with fault input

? Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)

? Serial Communications Interface (SCI)

? Two General Purpose Quad Timers with 2 external outputs

? 8K × 16-bit words (16KB) Program Flash

? 1K × 16-bit words (2KB) Program RAM

? 2K × 16-bit words (4KB) Data Flash

? 1K × 16-bit words (2KB) Data RAM

? 2K × 16-bit words (4KB) Boot Flash

? JTAG/OnCETM port for debugging

? On-chip relaxation oscillator

? 4 shared GPIO

? 32-pin LQFP Package

56F802 Features

Processing Core

? Efficient 16-bit 56800 family controller engine with dual Harvard architecture

? As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency

? Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

? Two 36-bit accumulators including extension bits

? 16-bit bidirectional barrel shifter

? Parallel instruction set with unique processor addressing modes

? Hardware DO and REP loops

? Three internal address buses and one external address bus

? Four internal data buses and one external data bus

? Instruction set supports both DSP and controller functions

? Controller style addressing modes and instructions for compact code

? Efficient C compiler and local variable support

? Software subroutine and interrupt stack with depth limited only by memory

? JTAG/OnCE debug programming interface