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Description

This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low.

Features

? 28-bit 1:2 registered buffer with parity check functionality

? Supports SSTL_18 JEDEC specification on data inputs and outputs

? Supports LVCMOS switching levels on CSGateEN and RESET inputs

? Low voltage operation: VDD = 1.7V to 1.9V

? Available in 160-ball LFBGA package

Applications

? DDR2 Memory Modules

? Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

? Ideal for DDR2 400, 533, 667, and 800