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OR2C12A中文資料
OR2C12A數(shù)據(jù)手冊規(guī)格書PDF詳情
Description
The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources.
Features
■ High-performance, cost-effective, low-power 0.35 μm CMOS technology (OR2CxxA), 0.3 μm CMOS technology (OR2TxxA), and 0.25 μm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade)
■ High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM)
■ Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis)
■ Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures
■ Eight 3-state buffers per PFU for on-chip bus structures
■ Fast, on-chip user SRAM has features to simplify RAM design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
■ Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers
■ Fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30 increase in speed
■ Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable
■ Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation
■ Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance
■ Upward bit stream compatible with the ORCA ATT2Cxx/ ATT2Txx series of devices
■ Pinout-compatible with new ORCA Series 3 FPGAs
■ TTL or CMOS input levels programmable per pin for the OR2CxxA (5 V) devices
■ Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source
■ Built-in boundary scan (IEEE*1149.1 JTAG) and 3-state all I/O pins, (TS_ALL) testability functions
■ Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP)
■ Full PCI bus compliance for all devices
■ Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ORCA Foundry Development System support (for back-end implementation)
■ New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI systems
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
OR2C12A產(chǎn)品屬性
- 類型
描述
- 型號
OR2C12A
- 功能描述
FPGA - 現(xiàn)場可編程門陣列 1296 LUT 288 I/O
- RoHS
否
- 制造商
Altera Corporation
- 系列
Cyclone V E
- 邏輯塊數(shù)量
943 內(nèi)嵌式塊RAM -
- EBR
1956 kbit
- 輸入/輸出端數(shù)量
128
- 最大工作頻率
800 MHz
- 工作電源電壓
1.1 V
- 最大工作溫度
+ 70 C
- 安裝風(fēng)格
SMD/SMT
- 封裝/箱體
FBGA-256
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
LATTICE(萊迪思) |
24+ |
SQFP-304(40x40) |
907 |
深耕行業(yè)12年,可提供技術(shù)支持。 |
|||
LATTICE |
23+ |
NA |
25060 |
只做進口原裝,終端工廠免費送樣 |
|||
LATTICE |
24+ |
QFP |
5000 |
全現(xiàn)原裝公司現(xiàn)貨 |
|||
LATTICE |
0022 |
2 |
公司優(yōu)勢庫存 熱賣中! |
||||
LATTICE |
22+ |
NA |
500000 |
萬三科技,秉承原裝,購芯無憂 |
|||
LATTICE(萊迪思) |
20+ |
- |
512 |
||||
LATTICE/萊迪斯 |
22+ |
NA |
18000 |
原裝現(xiàn)貨原盒原包.假一罰十 |
|||
ORCA |
25+ |
QFP |
12496 |
ORCA原裝正品OR2C12A-4S208即刻詢購立享優(yōu)惠#長期有貨 |
|||
LUCENT |
2023+ |
BGA256 |
2000 |
專注軍工、汽車、醫(yī)療、工業(yè)等方案配套一站式服務(wù) |
|||
ORCA |
24+ |
QFP |
8000 |
只做原裝正品現(xiàn)貨 |
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Datasheet數(shù)據(jù)表PDF頁碼索引
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