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Operating Conditions

? 1.62V - 3.63V, -40oC to +125oC, DC to 40 MHz (PIC32CM LE00/LS00)

? 1.62V - 3.63V, -40oC to +85oC, DC to 48 MHz (PIC32CM LE00/LS00)

? 2.0V - 3.63V, -40oC to +85oC, DC to 48 MHz (PIC32CM LS60)

Core

? Arm? Cortex?-M23 CPU running at up to 48 MHz:

– 2.64 CoreMark/MHz and 1.03 DMIPS/MHz

– Single-cycle hardware multiplier

– Hardware divider

– Nested Vector Interrupt Controller (NVIC)

– Memory Protection Unit (MPU)

– Stack Limit Checking

– TrustZone? for ARMv8-M (optional)

Memories

? 512/256/128 KB Flash

? 16/8/4 KB Data Flash Write-While-Read (WWR) section for non-volatile

data storage

? 64/32/16 KB SRAM

? Up to 512 bytes TrustRAM with physical protection features

? 32 KB Boot ROM

System

? Power-on Reset (POR) and programmable Brown-out Detection (BOD)

? Up to 16-channel Direct Memory Access Controller (DMAC)

? Up to 12-channel event system for Inter-peripheral Core-independent

Operation

? CRC-32 generator

Low-Power and Power Management

? Active, Idle, Standby with partial or full SRAM retention and off sleep

modes:

– Active mode (< 40 μA/MHz for PL0, < 60 μA/MHz for PL2)

– Idle mode (< 15 μA/MHz) with 1.5 μs wake-up time

– Standby with Full SRAM retention (1.7 μA) with 2.7 μs wake-up time

– Off mode (< 100 nA)

? Static and dynamic power gating architecture

? Sleepwalking peripherals

? Two performance levels

? Embedded Buck/LDO regulator with on-the-fly selection

Security and Safety

? Up to eight input pins and eight output pins for anti-tampering detections

? Data Flash

– Optimized for secure storage

– Address and Data Scrambling with user-defined key (optional)

– Tamper erase of scrambling key and of one user-defined row

– Silent access for data read noise reduction

? TrustRAM

– Address and Data scrambling with user-defined key

– Anti-tamper Active Shield on physical TrustRAM

– Tamper Erase of scrambling key and TrustRAM data

– Silent access for data read noise reduction

– Data remanence prevention

? Peripherals

– One True Random Number Generator (TRNG)

– AES-256/192/128, SHA-256, and GCM cryptography accelerators

(optional)

– Secure pin multiplexing capability to isolate secure communication

channels with external devices from the non-secure application

(optional)

? TrustZone for flexible hardware isolation of memories and peripherals

(optional)

– Up to five regions for the Flash

– Up to two regions for the Data Flash

– Up to two regions for the SRAM

– Individual security attribution for each peripheral, I/O, external

interrupt line, and Event System Channel

? SHA-based or HMAC-based secure boot (optional)

Security and Safety continued...

? ATECC608B-TFLXTLS CryptoAuthentication? device (optional)

– One Permanent Primary P-256 Elliptic Curve Cryptography (ECC)

Private Key

– One Internal Sign Private Key for Key Attestation

– Three Secondary P-256 ECC Private Keys

– Signer Public Key from Signer Certificate

– Public Key Validation Support

– One Customizable Symmetric Secret Key Slot

– I/O Protection Key Slot to Protect Communication

– Secure Boot Enabled with Customizable Secure Boot Public Key

– ECDH/KDF Key Slot Capable

– X.509 Compressed Certificate Storage

– Customizable Certificate Storage Slots

? Device Identity Composition Engine (DICE) security standard support with

Unique Device Secret (UDS) (optional)

? Up to three debug access levels

? Up to three chip erase commands to erase part of or the entire

embedded memories

? Unique 128-bit serial number

Timers/Output Compare/Input Capture

? Three 16-bit Timers/Counters (TC), each configurable as:

– One 16-bit TC with two compare/capture channels

– One 8-bit TC with two compare/capture channels

– One 32-bit TC with two compare/capture channels, by using two TCs

? Up to three 24-bit Timers/Counters for Control (TCC), with configurable

extensions:

– Fault Detection

– Dithering

– Dead-time insertion

– Pattern Generation

? One 16-bit Timers/Counter for Control (TCC), with fault detection support

? 32-bit Real-Time Counter (RTC) with clock/calendar functions

? PWM Outputs using TC and TCC peripherals:

– Up to eight PWM outputs on each 24-bit TCC0 and TCC3

– Up to four PWM outputs on 24-bit TCC1

– Up to two PWM outputs on 16-bit TCC2

– Up to two PWM outputs on each 16-bit TC

? Watchdog Timer (WDT) with Window mode

Communication Interfaces

? USB Full-Speed Device and Host

– Crystal-less operation in Device mode using DFLL48M

– Supports 8 IN endpoints and 8 OUT endpoints in Device mode, no

endpoint size limitations

– Supports 8 physical pipes in Host mode, no pipe size limitations

– Integrated serial resistors

? Up to six Serial Communication Interfaces (SERCOM) that can operate as:

– USART with full-duplex and single-wire half-duplex configuration

– I2C up to 3.4 Mbit/s (High-Speed mode)

– Serial Peripheral Interface (SPI)

– ISO7816

– RS-485

– LIN Host/Client

– ATECC608B-TFLXTLS CryptoAuthentication interface (optional)

? One Inter-IC Sound Interface (I2S) with up to 8-slot TDM and PDM

microphone support (optional)

Advanced Analog and Touch

? One 12-bit 1 MSPS Analog-to-Digital Converter (ADC) with up to 24

channels

? Up to four Analog Comparators (AC) with window compare function

? Two 12-bit 1 MSPS Digital-to-Analog Converter (DAC) that can operate as:

– Two independent DACs in Single-Ended mode

– One single DAC in Differential mode

? Three Operational Amplifiers (OPAMP)

? One enhanced Peripheral Touch Controller (PTC):

– Up to 32 self-capacitance channels

– Up to 256 (16 x 16) mutual-capacitance channels

– Low-power, high-sensitivity, environmentally robust capacitive

touch buttons, sliders, wheels, and trackpads

– Driven Shield Plus for better noise immunity and moisture

tolerance

– Parallel Acquisition (Boost Mode) through Polarity control

– Hardware noise filtering and noise signal desynchronization for

high conducted immunity

– Supports wake-up on touch from Standby Sleep mode

Clock Management

? Flexible clock distribution optimized for low power

? 32.768 kHz crystal oscillator (XOSC32K)

? 32.768 kHz ultra low-power internal RC oscillator (OSCULP32K)

? 0.4 to 32 MHz crystal oscillator (XOSC)

? 16/12/8/4 MHz low-power internal RC oscillator (OSC16M)

? 48 MHz digital Frequency-Locked Loop (DFLL48M)

? 32 MHz Ultra low-power digital Frequency-Locked Loop (DFLLULP)

? 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)

? Clock Failure Detection on both crystal oscillators (CFD)

? One frequency meter (FREQM)

Debugger Development Support

? Two-pin Serial Wire Debug (SWD) programming and debugging interface

? Four hardware breakpoints, two data watchpoints

Input/Output (I/O)

? Up to 80 programmable I/O lines

? Up to sixteen external interrupts (EIC)

? One non-maskable interrupt (NMI)

? Up to Four-LUTs Configurable Custom Logic (CCL) that supports:

– Combinatorial logic functions, such as AND, NAND, OR, and NOR

– Sequential logic functions, such as Flip-Flop and Latches

Software and Tools Support: Develop Prototypes Quickly With Our

Powerful, Easy-to-Use Ecosystem

? Get code off to a head start with MPLAB Code Configurator

? Graphically configure peripherals, software libraries, and supported RTOS

with MPLAB Harmony

? Download MPLAB? XC Compiler

? Take advantage of MPLAB X IDE's support for 32-bit MCUs

? Select the best debugger for the project: MPLAB ICE, MPLAB ICD, or

PICkit?