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Introduction

The SAMD21RT is a radiation tolerant, low-power microcontroller using the 32-bit Arm? Cortex?-M0+ processor,

64-pins with 128 KB Flash and 16 KB of SRAM. The SAMD21RT operates at a maximum frequency of 48 MHz

and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive migration with identical peripheral

modules, hex compatible code, identical linear address map, and pin compatible migration paths between

all devices in the product series. All devices include intelligent and flexible peripherals, Event System for interperipheral signaling, and support for capacitive touch button, slider, and wheel user interfaces.

The SAMD21RT provides the following features: In-system programmable Flash, 12-channel Direct Memory

Access Controller (DMAC), 12-channel Event System, programmable Interrupt Controller, 52 programmable I/O

pins, 32-bit Real-Time Clock and Calendar (RTC), five 16-bit Timer/Counters (TC) and four 24-bit Timer/Counters

for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate

program execution timing or input capture with time and frequency measurement of digital signals. The TCs

can operate in 8-bit or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters

have extended functions optimized for motor, lighting, and other control applications. The series provide one

full-speed USB 2.0 embedded host and device interface; six Serial Communication Modules (SERCOM) that each

can be configured to act as an USART, UART, SPI, I2C up to 3.4 MHz, SMBus, PMBus, and LIN client; two-channel

I

2S interface; twenty-channel 350 ksps 12-bit ADC with programmable gain and optional oversampling and

decimation supporting up to 16-bit resolution, one 10-bit 350 ksps DAC, four analog comparators with Window

mode, Peripheral Touch Controller (PTG) supporting up to 256 buttons, sliders, wheels, and proximity sensing;

programmable Watchdog Timer (WDT), brown-out detector and power-on Reset and two-pin Serial Wire Debug

(SWD) program and debug interface.

Accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system

clock. Different clock domains can be independently configured to run at different frequencies, enabling power

saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency

while reducing power consumption.

The SAMD21RT have two software-selectable sleep modes, Idle and Stand-by. In Idle mode, the CPU is stopped

while all other functions can be kept running. The Event System supports synchronous and asynchronous

events, allowing peripherals to receive, react to and send events even in Stand-by mode.

The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface

can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can useany communication interface to download and upgrade the application program in the Flash memory.

Features

? Processor

– Arm?

Cortex?

-M0+ CPU running at up to 48 MHz

? Single-cycle hardware multiplier

? Micro Trace Buffer (MTB)

? Memories

– 4 KB Read-While-Write (RWWEE) Flash section

– 128 KB in-system self-programmable Flash

– 16 KB SRAM Memory

? System

– Power-on Reset (POR) and Brown-out Detection (BOD)

– Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M)

and 48 MHz to 96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)

– External Interrupt Controller (EIC)

– 16 external interrupts

– One Non-maskable Interrupt (NMI)

– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

? Low Power

– Idle and Standby Sleep modes

? Peripherals

– 12-channel Direct Memory Access Controller (DMAC)

– 12-channel Event System

– Five 16-bit Timer/Counters (TC), configurable as either:

? One 16-bit TC with two compare/capture channels

? One 8-bit TC with two compare/capture channels

? One 32-bit TC with two compare/capture channels, by using two TCs

– Four 24-bit Timer/Counters for Control (TCC), with extended functions:

? Four compare channels with optional complementary output

? Generation of synchronized pulse width modulation (PWM) pattern across port pins

? Deterministic fault protection, fast decay and configurable dead-time between

complementary output

? Dithering that increase resolution with up to 5 bit and reduce quantization error

– PWM Channels using TC and TCC peripherals:

? Eight PWM channels on each 24-bit TCC

? Two PWM channels on each 16-bit TCC

? Two PWM channels on each 16-bit TC

– 32-bit Real Time Counter (RTC) with clock/calendar function

– Watchdog Timer (WDT)

– CRC-32 generator

– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface

? Embedded host and device function

? Eight endpoints

– Six Serial Communication Interfaces (SERCOM), each configurable to operate as either:

? USART with full-duplex and single-wire half-duplex configuration

? I2C up to 3.4 MHz

? SPI

? LIN client

– One two-channel Inter-IC Sound (I2S) interface

– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels

? Differential and single-ended input

? 1/2x to 16x programmable gain stage

? Automatic offset and gain error compensation

? Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution

– 10-bit, 350 ksps Digital-to-Analog Converter (DAC)

– Two Analog Comparators (AC) with Window Compare function

– Peripheral Touch Controller (PTC)

? Up to 256-Channel capacitive touch and proximity sensing

? I/O

– 52 programmable I/O pins

? Operating Conditions

– Supply voltage: 3.0V to 3.6V

– Operating temperature: -40 °C to +125 °C

? Packages

– CQFP, 64-lead, _g

– TQFP, 64-lead, _g

? Radiation Tolerance Data

– Total dose: 50 krad (Si)

Single Event Latch-up immunity > 78 MeV.cm2/mg (+125 °C)

Single Event Upset (SEU) Rate TBD

? ESD

– HBM: TBD

– CDM:

? TQFP64: TBD

? CQFP64: TBD