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DSP56852VFE中文資料
DSP56852VFE數(shù)據(jù)手冊規(guī)格書PDF詳情
Description
? 120 MIPS at 120MHz
? 6K x 16-bit Program SRAM
? 4K x 16-bit Data SRAM
? 1K x 16-bit Boot ROM
? 21 External Memory Address lines, 16 data lines and
four chip selects
? One (1) Serial Port Interface (SPI) or one (1) Improved
Synchronous Serial Interface (ISSI)
? One (1) Serial Communication Interface (SCI)
? Interrupt Controller
? General Purpose 16-bit Quad Timer
? JTAG/Enhanced On-Chip Emulation (OnCE?) for
unobtrusive, real-time debugging
? Computer Operating Properly (COP)/Watchdog Timer
? 81-pin MAPBGA package
? Up to 11 GPIO
1.1 Features
1.1.1Core
?Efficient 16-bit engine with dual Harvard architecture
?120 Million Instructions Per Second (MIPS) at 120MHz core frequency
?Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
?Four (4) 36-bit accumulators including extension bits
?16-bit bidirectional shifter
?Parallel instruction set with unique DSP addressing modes
?Hardware DO and REP loops
?Three (3) internal address buses and one (1) external address bus
?Four (4) internal data buses and one (1) external data bus
?Instruction set supports both DSP and controller functions
?Four (4) hardware interrupt levels
?Five (5) software interrupt levels
?Controller-style addressing modes and instructions for compact code
?Efficient C Compiler and local variable support
?Software subroutine and interrupt stack with depth limited only by memory
?JTAG/Enhanced OnCE debug programming interface
1.1.2Memory
?Harvard architecture permits as many as three simultaneous accesses to program and data memory
?On-chip memory includes:
—6K × 16-bit Program SRAM
—4K × 16-bit Data SRAM
—1K × 16-bit Boot ROM
?21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals
1.1.3Peripheral Circuits for DSP56852
?General Purpose 16-bit Quad Timer with two external pins*
?One (1) Serial Communication Interface (SCI)*
?One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module*
?Interrupt Controller
?Computer Operating Properly (COP)/Watchdog Timer
?JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
?81-pin MAPBGA package
?Up to 11 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
1.1.4Energy Information
?Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
?Wait and Stop modes available
DSP56852VFE產(chǎn)品屬性
- 類型
描述
- 型號
DSP56852VFE
- 功能描述
數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER
- RoHS
否
- 制造商
Microchip Technology
- 核心
dsPIC
- 數(shù)據(jù)總線寬度
16 bit
- 程序存儲器大小
16 KB 數(shù)據(jù) RAM
- 大小
2 KB
- 最大時鐘頻率
40 MHz
- 可編程輸入/輸出端數(shù)量
35
- 定時器數(shù)量
3
- 設(shè)備每秒兆指令數(shù)
50 MIPs
- 工作電源電壓
3.3 V
- 最大工作溫度
+ 85 C
- 封裝/箱體
TQFP-44
- 安裝風格
SMD/SMT
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
恩XP |
22+ |
81MAPBGA |
9000 |
原廠渠道,現(xiàn)貨配單 |
|||
恩XP |
21+ |
81-MAPBGA(8x8) |
800 |
100%全新原裝 亞太地區(qū)XILINX、FREESCALE-NXP AD專業(yè) |
|||
恩XP |
20+ |
BGA-81 |
1001 |
就找我吧!--邀您體驗愉快問購元件! |
|||
恩XP |
23+ |
81-LFBGA |
11200 |
主營:汽車電子,停產(chǎn)物料,軍工IC |
|||
Freescale(飛思卡爾) |
2022+ |
60000 |
原廠原裝,假一罰十 |
||||
FREESCAL |
23+ |
BGA81 |
19726 |
||||
FREESCALE |
BGA |
2170 |
正品原裝--自家現(xiàn)貨-實單可談 |
||||
Freesca |
2015+ |
BGA81 |
3526 |
原裝原包假一賠十 |
|||
FREESCALE |
23+ |
NA |
19960 |
只做進口原裝,終端工廠免費送樣 |
|||
FREESCA |
21+ |
12588 |
原裝正品,自己庫存 假一罰十 |
DSP56852VFE 資料下載更多...
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Datasheet數(shù)據(jù)表PDF頁碼索引
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