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Features

One Cortex?-A55 processor operating at up to 1.4 GHz

?32 KB L1 Instruction Cache

?32 KB L1 Data Cache

?256 KB L2 cache

?Media Processing Engine (MPE) with Arm? Neon? technology supporting the Advanced Single Instruction Multiple Data architecture

?Floating Point Unit (FPU) with support of the Arm? VFPv4-D16 architecture

Supports of 64-bit Arm? v8.2-A architecture

Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs

?Standard pixel formats commonly used in many camera input protocols

?Programmable resolutions up to 2K

?Image processing for:

—Supports one source of up to 2K horizontal resolution

—Supports pixel rate up to 200 Mpixel/s

?Image down scaling via decimation and bi-phase filtering

?Color space conversion

?Interlaced to progressive conversions

Boot ROM (256 KB) for Cortex?-A55

On-chip RAM (384 KB)

16-bit DRAM interface support at up to :

?LPDDR4 with inline ECC

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

?One eMMC 5.1 (8-bit) compliance with HS400 DDR signaling to support up to 400 MB/sec

?One SDXC (4-bit, no eMMC 5.1, with extended capacity)

?One SDIO (4-bit, SD/SDIO 3.01 compliance with 200 MHz SDR signaling and up to 100 MB/sec)

FlexSPI Flash with support for XIP (for Cortex?-A55 in low-power mode) and support for either one Octal SPI or Quad SPI FLASH device. It also supports both Serial NOR and Serial NAND flash using the FlexSPI.

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient power management

Trusted Resource Domain Controller (TRDC)

?Supports 16 domains

Arm? TrustZone? (TZ) architecture, including both TrustZone-A

On-chip RAM (OCRAM) secure region protection using OCRAM controller

EdgeLock? secure enclave

Battery Backed Security Module (BBSM)

?Secure Non-Volatile Storage (SNVS)

?Secure real-time clock (RTC)

Arm? CoreSight? debug and trace technology

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for single core Cortex?-A55

Cross Triggering Interface (CTI)

Support for 4-pin (JTAG) debug interface and SWD