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General description

The LPC55S3x is an ARM Cortex-M33 based microcontroller for embedded applications.

These devices include a Edge Lock Subsystems (ELS), Public Key Cryptography (PKC)

module, up to 256 KB on-chip flash, up to 128 KB of on-chip SRAM, FlexSPI with cache

and dynamic decryption, PRINCE module for on-the-fly flash encryption/decryption, USB

Full-Speed device with crystal-less operation, USB Full-Speed Host, CAN FD, five

general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate

Timer (MRT), a Windowed Watchdog Timer (WWDT), Code Watchdog Timer, one OS

Timer, one Micro-tick timer, eight flexible serial communication peripherals (Flexcomm

Interfaces - which can be configured as a USART, SPI, high speed SPI, I2C, or I2S

interface), one DMIC, one I3C interface, four 16-bit 2.0 Msamples/sec (four 12-bit 3.2

Msamples/sec) ADC capable of four simultaneous conversions, four comparators, two

temperature sensors, three 12-bit 1 Msample/sec DAC, 3 OpAmps, two FlexPWM timers,

and two QEIs.

The ARM Cortex-M33 provides a security foundation, offering isolation to protect valuable

IP and data with TrustZone? technology. It simplifies the design and software

development of digital signal control systems with the integrated digital signal processing

(DSP) instructions. To support security requirements, the chip also offers support for

secure boot, HASH, AES, Elliptic Curve Cryptography (ECC), RSA, UUID, DICE, dynamic

encrypt and decrypt, debug authentication, and is designed per TBSA specifications.

Features and benefits

? ARM? Cortex-M33 core (r0p4):

? Running at a frequency of up to 150 MHz.

? Integrated digital signal processing (DSP) instructions.

? TrustZone?, Floating Point Unit (FPU) and Memory Protection Unit (MPU).

? ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).

? Non-maskable Interrupt (NMI) input with a selection of sources.

? Serial Wire Debug with eight breakpoints and four watch points. Includes Serial

Wire Output for enhanced debug capabilities and trace (ETM).

? System tick timer.

? A hardware DSP accelerator for fixed and floating point DSP functions (PowerQuad).

PowerQuad uses a bank of four dedicated 4 KB SRAMs

? Crypto accelerator module PKC (Public Key Cryptography) uses a bank of 4 KB

SRAMs that are also AHB accessible by the CPU and the DMA engine.

? On-chip memory:

? Up to 256 KB on-chip flash program memory, with flash accelerator and 512 byte

page erase and write, coupled with 8 KB Low Power Cache to enhance system

performance.

? Up to 128 KB total SRAM consisting of 16 KB SRAM on Code Bus, 112 KB SRAM

on System Bus (112 KB is contiguous).

? Parity support on all RAM banks except RAM1 bank. ECC support available only

on RAM1 bank.

? OTP eFuse programmable memory.

? PRINCE module for real-time encryption of data being written to on-chip flash and

decryption of encrypted flash data during read to allow asset protection, such as

securing application code, and enabling secure flash update. External memory can be

encrypted, and the content being decrypted on-the-fly while the controller is fetching

data from the external memory.

? On-chip ROM bootloader supports:

? Booting of images from on-chip flash and external flash.

? CRC32 image integrity checking.

? Flash programming through In System Programming (ISP) commands over

following interfaces: USB0 interfaces using HID Class device, UART interface

(Flexcomm 0) with auto baud, High-Speed SPI slave interfaces (Flexcomm 8)

using mode 3 (CPOL = 1 and CPHA = 1), I2C slave interface (Flexcomm 1), and

CAN-FD ISP.

? ROM API functions:

Flash programming API and OTP eFuse programming API.

Protected Flash Region (PFR) programming and Secure firmware update API

using NXP Secure Boot file format, version 3.1 (SB3 files).

? PRINCE IP to define up to three encrypt/decrypt internal flash regions. Inline Prince

Encryption/Decryption (IPED) IP to define up to four encrypt/decrypt external flash

regions.

? NXP Debug Authentication Protocol version 2.0 (ECDSA P-256 signature

verification using ECC keys) version 2.1 (ECDSA P-384 signature verification using

ECC keys).

? Setting a sealed part to Fault Analysis mode through Debug authentication.

? Dual images (boot latest version) from on-chip flash using re-map feature.

? Loading image to RAM from external Octal/QuadSPI device.

? Booting Execute-in-Place (XIP) images present on Octal/QuadSPI devices.

? Dual Execute-in-Place (XIP) images in Octal/QuadSPI flash through flash address

remap feature.

? Load-to-RAM boot mode from 1-bit SPI flash devices connected to Flexcomm

(selectable by PFR) as normal boot option and recovery boot option.

? USB Device DFU Connection (Device only).

? Code Read protection (CRP) on non-secure devices.

? Crystal-less USB ISP Device mode.

? Secure Boot support:

? Uses ECDSA signature of SHA-2 digest as cryptographic signature verification.

? ECDSA secp256r1 (NIST P-256), SHA-256.

? ECDSA secp384r1 (NIST P-384), SHA-384.

? Uses custom certificate format to validate image public keys.

? Up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust

establishment by storing the SHA-2 hash digest of the hashes of up to four RoT

public keys in protected flash region (PFR).

? Anti-rollback feature using image key revocation and supports up to 32

IMAGE_KEY_REVOKE field form CFPA and constraint field from ISK certificate.

? Enforces anti-rollback check during boot and firmware update using Secure_FW_

Version, a 32-bit monotonic counter, in CFPA.

? Image key certificate revocation using IMAGE_KEY_REVOKE, a 32-bit monotonic

counter in CFPA. Allowing up to 4,294,967,295 image key revocations.

? PFR authentication using OTP eFuse and CMAC computed using DUK (Device

Unique Key).

? Image authentication APIs and authentication of XIP images.

? Secure boot using ECDSA P-256/P-384 signed images.

? Booting of SB3.1 signed AES & encrypted images over serial interfaces (UART,

I2C, SPI-slave, USB-HID).

? SB commands to program flash, OTP eFuse, PFR, PUF provisioning, QSPI flash

programming, write to RAM and execute RAM (after image authentication). SB

commands in recovery boot supports commands including flash/PFR/OTP eFuse

programming.

? SB3 firmware update APIs.

? Boot ROM supports Device Identifier Composition Engine (DICE) Specification

(version Family 2.0, Level 00 Revision 69) specified by Trusted Computing Group.

? Serial interfaces:

? Flexcomm Interface contains up to eight serial peripherals (Flexcomm Interface

0-7). Each Flexcomm Interface can be selected by software to be a USART, SPI,

I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports

USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm

Interface, including a shared fractional baud-rate generator, and time-out

feature.Flexcomm interfaces 0 to 5 each provide one channel pair of I2S and

Flexcomm interfaces 6 to 7 each provide four channel pairs of I2S.

? I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.

? High Speed SPI (Flexcomm 8, 50MHz for both master and slave).

? A digital microphone interface supporting up to two channels with associated

decimators and Voice Activation Detect. One pair of channels can be streamed

directly to I2S. The DMIC supports DMA.

? One I3C bus interface.

? One CAN FD module with dedicated DMA controller.

? USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode using software library

example in Application Note (AN13527, LPC55S3x/LPC553x Crystal-Less USB

Solution).

? Digital peripherals:

? DMA0 controller with 52 channels and up to 53 programmable triggers, able to

access all memories and DMA-capable peripherals.

? DMA1 controller with 16 channels and up to 25 programmable triggers, able to

access all memories and DMA-capable peripherals.

? CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials with DMA support. Supports programmable CRC polynomial.

? Up to 66 General-Purpose Input/Output (GPIO) pins.

? GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.

? Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.

? A group of up to 8 GPIO pins can be selected for boolean pattern matching, which

can generate interrupts and/or drive a pattern-match output.

? Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

? I/O pin configuration with support for up to 16 signal options.

? FlexSPI flash interface for external flash with 8 KB cache and dynamic decryption

for execute-in-place and supports DMA. The FlexSPI includes 1 port: high speed

channel A which supports quad or octal operation. Support dual image via address

remapping.

? Two AOI (AND/OR/Invert) combinatorial logic modules with dedicated set of input

and output signals. Each AOI has 4 outputs that feed to different peripheral muxes

to individual peripherals.

? Security Features:

? ARM TrustZone? enabled.

? AES-256 encryption/decryption engine with keys fed directly from PUF or a

software supplied key. Supports AES-GCM mode.

? Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA

controller.

? Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint.

PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes

hardware for key extraction.

? Secure GPIO.

? Device Identifier Composition Engine (DICE).

? True Random Number Generator (TRNG).

? Enhanced Tamper Detection

? Tamper Detection to detect illegal access into the system.

? Tamper sources can be individually enabled/disabled and polarity can be

controlled.

? Supports four External tamper sources which filtered for noise & glitches by the

RTC.

? A tamper queue is implemented in the design to store the tamper type and time

stamp (excluding the year value) of the tampers.

? 128 bit unique device serial number for identification (UUID).

? Timers:

? Five 32-bit standard general purpose asynchronous timers/counters, which support

up to four capture inputs and four compare outputs, PWM mode, and external

count input. Specific timer events can be selected to generate DMA requests.

? One SCTimer/PWM with 8 input and 10 output functions (16 capture and match

registers). Inputs and outputs can be routed to or from external pins and internally

to or from selected peripherals. Internally, the SCTimer/PWM supports 16

captures/matches, 16 events, 32 states, and a Dither engine for improved average

resolution of pulse edges.

? 32-bit Real-time clock (RTC) with calendar feature and 1 s resolution running in the

always-on power domain. Another timer in the RTC can be used for wake-up from

all low power modes including deep power-down, with 1 ms resolution. The RTC is

clocked by the 32 kHz FRO or 32.768 kHz external crystal.

? Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

? Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.

? Code Watchdog for detecting code flow integrity.

? The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up

the device from sleep and deep-sleep modes. Includes 4 capture registers with pin

inputs.

? 42-bit free running OS Timer as continuous time-base for the system, available in

any reduced power modes. It has a selectable clock source. When a 32 kHz clock

is selected, allows a count period of more than 4 years.

? Motor Control Subsystem: 2x FlexPWM with 4 sub-modules, providing 24 PWM

outputs (it supports two 3-phase motors), and 2 Quadrature Encoder/Decoder (QEI).

? Analog peripherals:

? Four single-ended 16-bit or two differential input ADCs (selectable) with sample

rate of 2.0 Msamples/sec in 16-bit mode and 3.2 Msamples/sec in 12-bit mode.

Eight differential channel pairs, (or 16 single-ended channels), with multiple internal

and external trigger inputs. The ADC supports four simultaneous conversions,

under the control of two independent sequences.

? Integrated temperature sensor connected to both ADCs.

? One comparator in always-on domain with up to four input pins and internal

reference voltage. Can be used as a wake-up source from low power modes.

? Three High Speed Comparators with up to five input pins and internal reference

voltage.

? Three 12-bit DACs with sample rates of up to 1.0 MSample/sec.

? Three OpAmps with programmable VREF.

? Clock generation:

? Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96

MHz output, and a 12 MHz output (divided down from the selected higher

frequency) that can be used as a system clock. The FRO is trimmed to +/- 1%

accuracy over the entire voltage and 0 C to 85 C. The FRO is trimmed to +/- 2%

accuracy over the entire voltage and -40 C to 105 C.

? 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2%

accuracy over the entire voltage and temperature range.

? Internal low power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the

entire voltage and temperature range.

? Crystal oscillator with an operating frequency of 16 MHz to 32 MHz. Option for

external clock input (bypass mode) for clock frequencies of up to 25 MHz.

? Crystal oscillator with 32.768 kHz operating frequency.

? PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the

need for a high-frequency external clock. PLL0 and PLL1 can run from the internal

FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the

32.768 kHz RTC oscillator.

? Clock output function with divider to monitor internal clocks.

? Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

? Each crystal oscillator has one embedded capacitor bank, where each can be used

as an integrated load capacitor for the crystal oscillators. Using APIs, the capacitor

banks on each crystal pin can tune the frequency for crystals with a Capacitive

Load (CL) leading to conserving board space and reducing costs.

? Power-saving modes and wake-up:

? Integrated PMU (Power Management Unit) to minimize power consumption.

? Low power modes: Sleep, Deep-sleep with RAM retention, power-down with RAM

retention and CPU retention, and deep power-down with RAM retention.

? Configurable wake-up options from peripherals interrupts.

? The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up

the device from sleep and deep-sleep modes.

? The Real-Time Clock (RTC) running from the 32.768 kHz clock can be used to

wake-up the device from sleep, deep-sleep, power-down, and deep power-down

modes.

? Power-On Reset (POR) (trip low-level of 0.705 V and trip high-level of 0.87 V).

? Brown-Out Detectors (BOD) for external VDD_MAIN and internal VDD_CORE with

separate thresholds for forced reset.

? Operating from internal DC-DC converter or selectable LDO such that DC-DC

converter can be bypassed.

? On-chip LDO core 1.8 V to 3.6 V.

? DC-DC power supply 1.8 V to 3.6 V.

? Two Main IO supplies (VDDIO_1: 1.8 V to 3.6 V, VDDIO_2: 1.08 v to 3.6 V).

? Separate VBAT supply 1.71 V to 3.6 V.

? JTAG boundary scan supported.

? Operating temperature range ?40 °C to +105 °C.

? Available in HLQFP100, and HVQFN48 packages.