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SMJ: QML Processing to MIL?PRF?38535

TMP: Commercial Level Processing

Operating Temperature Ranges:

? Military (M) ?55°C to 125°C

? Commercial (C) ?25°C to 85°C

? Commercial (L) 0°C to 70°C

Highest Performance Floating-Point Digital

Signal Processor (DSP)

? ’C40-50:

40-ns Instruction Cycle Time:

50 MFLOPS, 25 MIPS, 275 MOPS,

320 MBps

? ’C40-40:

50-ns Instruction Cycle Time:

40 MFLOPS, 20 MIPS, 220 MOPS,

256 MBps

Six Communications Ports

6-Channel Direct Memory Access (DMA)

Coprocessor

Single-Cycle Conversion to and From

IEEE-745 Floating-Point Format

Single Cycle 1/x, 1/

Source-Code Compatible With SMJ320C30

Validated Ada Compiler

Single-Cycle 40-Bit Floating-Point,

32-Bit Integer Multipliers

12 40-Bit Registers, 8 Auxiliary Registers,

14 Control Registers, and 2 Timers

IEEE Standard 1149.1? Test-Access Port

(JTAG)

Two Identical External Data and Address

Buses Supporting Shared Memory Systems

and High Data-Rate, Single-Cycle

Transfers:

? High Port-Data Rate of 100 MBytes/s

(Each Bus)

? 16G-Byte Continuous

Program/Data/Peripheral Address Space

? Memory-Access Request for Fast,

Intelligent Bus Arbitration

? Separate Address-, Data-, and

Control-Enable Pins

? Four Sets of Memory-Control Signals

Support Different Speed Memories in

Hardware

Fabricated Using Enhanced Performance

Implanted CMOS (EPIC?) Technology by

Texas Instruments (TI?)

Separate Internal Program, Data, and DMA

Coprocessor Buses for Support of Massive

Concurrent Input/Output (I/O) of Program

and Data Throughput, Maximizing

Sustained Central Processing Unit (CPU)

Performance

On-Chip Program Cache and

Dual-Access/Single-Cycle RAM for

Increased Memory-Access Performance

? 512-Byte Instruction Cache

? 8K Bytes of Single-Cycle Dual-Access

Program or Data RAM

? ROM-Based Bootloader Supports

Program Bootup Using 8-, 16-, or 32-Bit

Memories Over Any One of the

Communications Ports

description

The TMP/SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-μm, double-level

metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world’s first

DSP designed for parallel processing. The on-chip parallel processing capabilities of the ’C40 make the

floating-point performance required by many applications achievable and cost-effective.

The TMP/SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor

communication using simple communication software with no external hardware. This allows connectivity with

no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA

coprocessor is able to handle the CPU I/O requirements.