精品国产99久久久久久www_亚洲精彩视频在线观看的_性欧美婬妇ⅹxxx视频_里番肉工口全彩老师_a天堂最新在线观看_精品国产在天天在线观看_免费看那种视频_樱桃电视剧全集播放_成人性视频免费看的鲁片_中国伦理影院

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low.

Features

? 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality

? Supports SSTL_18 JEDEC specification on data inputs and outputs

? Supports LVCMOS switching levels on C0, C1, and RESET inputs

? Low voltage operation: VDD = 1.7V to 1.9V

? Available in 96-ball LFBGA package

Applications

? DDR2 Memory Modules

? Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

? Ideal for DDR2 667 and 800